1. Field of the Invention
The present invention relates to an input circuit of a semiconductor device and, more specifically, to an input circuit whose inner circuitry is free from the influence of surge voltage of input signals.
2. Description of the Background Art
FIG. 10 is a schematic block diagram of a semiconductor device to which the present invention is applied. Referring to FIG. 10, a semiconductor integrated circuit device 31 to which the present invention is applied receives external signals at external input terminals 32 and the signals are transmitted to the internal circuitry through input protecting circuits 33. As shown in FIG. 10, generally, circuits called input protecting circuits 33 are provided between the external input terminals 32 and the internal circuit so as to prevent breakdown of the internal circuit caused by a surge voltage from the external input terminals 32, in the semiconductor integrated circuit device 31.
The present invention is to prevent problems caused by introduction of electrons or the like at portions where the input signal is connected to the substrate through a diffusion layer and a well layer when a surge voltage such as undershoot is applied to the external input terminal 32, and the present invention is not particularly related to the input protecting circuit 33 shown in FIG. 10. The details of the input circuit is disclosed in, for example, U.S. Pat. No. 4,692,781 entitled "Semiconductor Device With Electrostatic Discharge Protection".
Problems caused by the undershoot, for example, on the semiconductor device will be described in the following with reference to FIG. 11. FIG. 11 is a schematic diagram of a DRAM as an example of the semiconductor device. Referring to FIG. 11, the dynamic RAM (hereinafter referred to as a DRAM) comprises an input circuit 40 and a plurality of memory cells 43. The input circuit 40 comprises an N.sup.+ diffusion layer 47 and an input terminal 46 connected to the N.sup.+ diffusion layer 47. The memory cell 43 comprises an NMOS transistor 44 and a capacitor 45. The N.sup.+ diffusion layer 47 is connected to the input terminal 46. Further, the N.sup.+ diffusion layer 47 forms a part of the NMOS transistor 42 for discharging, when a high voltage is applied, the high voltage.
In the DRAM having such a structure, an undershoot of an input signal, for example, significantly affects the memory cell characteristics. For example, referring to FIG. 11, if an undershoot of the input signal is supplied as an input through the input terminal 46, electrons, which are minority carriers, are introduced to the P type semiconductor substrate 41 as shown by the dotted line in the figure. The electrons reach the memory cell 43 to destroy charges representing information stored in the memory cell 43. If the memory cell 43 and the input circuit 40 are adjacent to each other, the introduced electrons easily reach the memory cell 43 to incur this phenomenon. In order to prevent such a phenomenon, the distance between the memory cell 43 and the input circuit 40 is made sufficiently long, and generally, a substrate voltage generating circuit is provided on the semiconductor substrate 41 to apply a negative voltage V.sub.BB to the substrate.
FIG. 12 shows one example of a conventional input circuit. Referring to FIG. 12, the conventional input circuit 40 comprises a P type semiconductor substrate 1, a P well 2 formed on a main surface of the P type semiconductor substrate 1 and an N well 3 formed adjacent to the P well 2. On the main surface of the P well 2, an N.sup.+ diffusion layer 8 and an NMOS transistor 5 adjacent to the N.sup.+ diffusion layer 8 and connected to the ground potential are formed. An input terminal 7 is connected to the N.sup.+ diffusion layer 8, and an input resistance 6 exists in an interconnecting layer therebetween. An input signal is transmitted from the interconnecting layer connecting the input terminal 7 and the N.sup.+ diffusion layer 8 to the internal circuit. In the conventional input circuit 40, a parasitic bipolar transistor 4 is formed by the N.sup.+ diffusion layer 9, the P well 2 and the N.sup.+ diffusion layer 8. A negative voltage V.sub.BB is applied by the substrate voltage generating circuit to the P type semiconductor substrate 1. Generally, the substrate potential V.sub.BB is about -3 V.
The operation of the conventional input circuit 40 will be described. An external input signal is applied through the input terminal 7 and transmitted to the internal circuit through the input resistance 6 as well as to the N.sup.+ diffusion layer 8. The NMOS transistor 5 has a very thick gate oxide film, and the gate potential is 0 V, and therefore it is normally off. However, when a high electrostatic pulse is applied to the input terminal and a high voltage is applied to the N.sup.+ diffusion layer 8, a punch through phenomenon occurs in the NMOS transistor 5 so that the transistor is turned ON, whereby the high voltage is discharged to the ground potential and gate breakdown or the like is prevented in the internal circuit. When an overshoot is applied to the N.sup.+ diffusion layer 8, the P-N junction between the N.sup.+ diffusion layer 8 and the P well 2 is reversely biased, so that electrons are not introduced to the semiconductor substrate 1.
When an undershoot is applied to the N.sup.+ diffusion layer 8, introduction of electrons to the substrate 1 can be prevented until the undershoot reaches - (.vertline.V.sub.BB .vertline.+V.sub.D) V where diffusion potential of the P-N junction is represented as V.sub.D, since the P-N junction between the N.sup.+ diffusion layer 8 and the P well 2 is reversely biased, as the negative voltage V.sub.BB is applied to the substrate 1. For example, if V.sub.D =0.8 V and V.sub.BB =-3 V, introduction of electrons to the substrate can be prevented when the undershoot is up to about -3.8 V. However, if a plurality of DRAMs are mounted on a board and they are to be operated in the system, an undershoot exceeding this value may be applied to the DRAMs. In such a case, a forward direction voltage is biased to the P-N junction between the above mentioned N.sup.+ diffusion layer 8 and the P well 2. Consequently, electrons are introduced to the substrate, which may destroy the information stored in the memory cell. In addition, introduction of the electrons to the substrate also affects the substrate potential itself, which may affect refresh characteristic which is an important characteristic of the DRAM, degrade soft error rate, and cause fluctuation of transistor characteristics such as the threshold value V.sub.TH of the memory transistor, current supplying capability .beta. of the memory transistor, and so on. Therefore, in the conventional input circuit, not only is a negative voltage V.sub.BB applied to the substrate but the parasitic bipolar transistor 4 is utilized to prevent introduction of electrons to the substrate. More specifically, referring to FIG. 12, a region formed of an N.sup.+ diffusion layer 9 and an N well 3 is formed, and the potential of this region is fixed to the supply voltage V.sub.CC. By providing such a region, a parasitic bipolar NPN transistor 4 is formed between the N.sup.+ diffusion layer 9, the N well 3, the P well 2 and the N+ diffusion layer 8. An equivalent circuit thereof is shown in FIG. 13.
Referring to FIG. 13, the operation of the parasitic bipolar NPN transistor 4 will be described. If an undershoot whose absolute value is smaller than (.vertline.V.sub.BB .vertline.+V.sub.D) V is applied to the N.sup.+ diffusion layer 8, the parasitic bipolar transistor 4 is OFF. However, if an undershoot whose absolute value exceeds (.vertline.V.sub.BB .vertline.+V.sub.D) V is applied, the parasitic bipolar transistor 4 is turned ON. In principle, the electrons introduced from the N.sup.+ diffusion layer 8 hardly flow to the substrate, but flow to the supply voltage V.sub.CC through the N.sup.+ diffusion layer 9. However, actually, the parasitic bipolar transistor 4 has wide base, so that part of the electrons introduced from the N.sup.+ diffusion layer 8 flow to the substrate 1.
FIG. 14 is a timing chart showing relation between an undershoot of the input signal described above and the current flow to the substrate 1 at that time. Reference numeral (1) of FIG. 14 represents voltage of the input signal applied to the external input terminal 7, (2) represents current flowing through the P-N junction portion, and (3) represents current flowing through the substrate 1. If an undershoot of the input signal occurs from the time t.sub.0 and the value thereof exceeds a prescribed value, a current as shown in the figure flows through the P-N junction and the current as shown in the figure flows to the substrate 1 (from t.sub.1 to t.sub.2).
Consequently, in the conventional input circuit, destruction of information stored in the memory cells, degradation of refresh characteristic and soft error rate caused by fluctuation of the substrate voltage, malfunctions caused by fluctuation of transistor characteristics derived from fluctuation of the substrate voltage and so on caused by electrons introduced by an undershoot or an overshoot of the input circuit can not be perfectly prevented, and the operation of the internal circuit in the semiconductor device is unstable.